1. Field of the Invention
The present invention relates to the field of manufacturing thin films using spin-on methods. Specifically, this invention relates to (1) the manufacture of low dielectric constant layers for insulation of metal interconnects in semiconductor devices and (2) photoresist layers. More specifically, the invention relates to apparatus for and methods for improving the quality of spin-on thin films, including the use of a processor to regulate the deposition of spin-on films.
2. Discussion of the Related Art
Spin-on deposition methods are used for the manufacture of thin films on semiconductor devices. Generally, a solution comprising a solvent and a precursor of the material to be deposited is placed in the center of a semiconductor wafer and then the wafer is rotated at a rate sufficient to distribute the solution across the surface of the wafer (a "rapid spin step"). The amount of solution, the solution viscosity, the solvent evaporation rate, the acceleration and the maximum spinning speed determine, in general, the thickness of the spin-on coating.
The deposition of low dielectric constant materials such as glass and glass-like materials have also been deposited by spin-on methods. These spin-on-glass (SOG) methods generally involve the placement of a pool or puddle of a solution comprising a silicate or other precursor and an solvent such as an alcohol on the center of a semiconductor wafer. Typically, for a wafer with a diameter of 8 inches, about 4 ml of solution is used. The wafer is then rotated to distribute the solution over the wafer surface. During spinning, as the solvents evaporate, residual material, including by way of example only, an SiO.sub.2 -like layer, is deposited on the wafer. Typically, spin-on processes have been carried out at atmospheric pressure under ambient conditions, such as in air. For certain precursor solutions containing solvents with high volatility, solvent can evaporate so rapidly as to cause the spin-on layer to solidify before all of the thinning and evening steps have been completed. For these materials, the resulting spin-on layers are not ideally suited for manufacture of semiconductor devices. Layers deposited in this fashion can have non-uniformities of 20% or greater when deposited on patterned wafers with metal interconnects. For future integrated circuit manufacture, however, this non-uniformity presents a significant problem. This is true especially in the manufacture of multi-layered films. Each layer contributes its own nonuniformity to the multilayered film, and because the nonuniformity tends to be in the form of a thicker layer at the center of the wafer, the overall nonuniformity increases with the number of layers.
As a result of these problems, these processes are suitable for the manufacture of semiconductor devices with gap dimensions of greater than 0.5 .mu.m. For purposes of this application, the term gap dimensions means the distance separating integrated circuit elements, for example, metal lines. Thus, filling the gaps between semiconductor elements requires that the deposition process provide dielectric material which can penetrate into the recesses of the gap. Conventional spin-on methods are not suited for manufacturing devices with gap dimensions of less than 0.5 .mu.m. First, dispensing of a puddle of solution onto the middle of the wafer creates less complete coverage at the edges of the wafer. To counteract this problem, the puddle typically includes substantially more solution than is necessary to provide an even layer of solution over the wafer. During the rapid spinning step, more of the solution is spun off of the wafer, resulting in substantial loss of expensive precursors and environmentally harmful solvents. Next, as gaps in the metal interconnect pattern become narrower, it is more difficult to evenly fill the gaps, especially as the solution is distributed radially across the surface with a high velocity. Furthermore, as the solution is distributed radially, the solvent evaporates from the solution. This can lead to changes in the concentration of precursor in the solution and/or the viscosity of the solution as it is being distributed across the wafer.
These features of the prior art methods result in poor planarity of the surface, which can reduce the accuracy of subsequent manufacturing steps. The resulting semiconductor devices then can have low reliability. These problems have limited the minimum size of features which can be coated using spin-on methods.
Conventional solutions to these problems included the use of greater amounts of spin-on solution or the use of longer spin times. However, the use of more solution results in higher losses of chemicals, and longer spin times reduces the through-put in the wafer manufacturing process.
Certain types of dielectric materials can be cross-linked after deposition to increase the mechanical strength of the resulting thin film. However, prior art methods usually involve rapid temperature increases, which can result in thermomechanical stress being placed on the film. Mechanical stresses can weaken the film and can lead to increases in dielectric constant and decreased dielectric strength. These effects can result in decreased useful lifetimes of the thin films.